In their ongoing effort to obtain smaller, faster and more efficient semiconductor devices, designers and engineers have attempted to reduce the scale of all the dimensions and features of the devices. In the design and manufacture of field-effect transistors (FETs) particularly, it has been found that two features are difficult to scale down: the device current (which is related to the size of the FET gate) and the size of fuse structures.
To address device scaling limitations in gate design, considerable work has recently been done to develop manufacturable methods to create novel types of gates. One example of a “dual gate” or “wrap-around gate” design is the FINFET device, where the gate oxide is grown on the face of a vertical fin of silicon and the gate is on both sides of the silicon feature, which when activated fully depletes the silicon. FIG. 1A shows two such fin structures 1, 2 formed on a silicon-on-insulator (SOI) substrate, where the top of the bulk silicon substrate 10 has a buried oxide (BOX) layer 3 formed thereon, and the devices are made in a further silicon layer overlying the BOX. Silicon fins 11, 21 are shown after being formed by etching of this silicon layer down to the BOX surface, using an etching hardmask 12, 22 for image transfer. A gate oxide may then be grown on both faces of a silicon fin (such as faces 11a and 11b of fin 11). The FINFET technology shows promise in offering higher areal gate density than more conventional planar CMOS devices, as well as better device performance, and lower power consumption.
It is also desirable to incorporate the manufacture of fuses and antifuses into existing processes for creating the various FET structures. As is known in the art, fuses are conductors which may easily be removed (“blown”) to create open circuits, while antifuses are areas of dielectric which may be electrically broken down to form a permanent conducting path. As the density of devices on a chip increases, the number of fuses and antifuses increases in order to provide specific addressing of each individual circuit. Fuses and antifuses are preferably formed with minimal expense of chip area and require no additional lithographic steps. Recent scaling of fuses has not kept up with the scaling rate of the rest of the silicon features, so that chip regions devoted to fuses are occupying a larger percentage of the total chip area.
If devices are formed with shallow-trench isolation (STI), etching of the isolation trench may create sharp corners in the silicon where the sidewall of the trench meets the top silicon surface or the trench bottom. If these corners are not rounded by further processing, a dielectric layer overlying the corners may be thinned and present reliability problems (see U.S. Pat. No. 6,150,234). Similarly, etching of a contact hole through a dielectric layer may result in a trench with sharp corners. On the other hand, a sharp trench corner presents an opportunity to conveniently form antifuses (the trench being etched in a conductive material or being coated with a conductive material), since the electric field is generally enhanced at the corner; while an insulating layer overlying the corner is thinned (see U.S. Pat. No. 5,502,000; U.S. Pat. No. 5,322,812; U.S. Pat. No. 6,096,580 and references cited therein; and Chen et al., IEEE Electron Device Letters 13, 53 (1992)).
Because significantly less chip area is required, it is preferable to fabricate electrical fuses rather than mechanical fuses as part of the transistor fabrication process. Conventional fuses are “blown” via laser ablation or other mechanical means to create an electrical open. Electrical fuses or antifuses are “blown” via internal electrical wiring in the chip; the area requirement for electrical fuses/antifuses is therefore much less. In addition, mechanical fuses require a protection region around and below them, to prevent the fuse-blowing technique from having other detrimental impacts on the chip circuits. Electrical fuses and antifuses do not have this requirement. To save chip area and thus reduce manufacturing cost, it therefore is desirable to fabricate electrical fuses or antifuses which may be integrated with fabrication of FINFET and planar CMOS devices, with a minimum number of additional fabrication steps.